Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Microchip Technology/ATSAMV71J20/TC0/TC_CHANNEL[0]/IER#0x0
Interrupt Enable Register (channel = 0)
Counter Overflow
Load Overrun
RA Compare
RB Compare
RC Compare
RA Loading
RB Loading
External Trigger
https://github.com/cmsis-svd/cmsis-svd-data